1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory device with a divided precharge control scheme capable of realizing high-speed access with a low power supply voltage.
2. Description of the Related Art
As the integration densities of semiconductor memory devices continues to increase, there is a continuing need to reduce the power supply voltages to the semiconductor memory devices to, among other things, minimize total power consumption and compensate for the smaller sizes of the discrete devices therein. In particular, in order to scale the size of MOS devices contained on a memory integrated circuit (IC), it is typically necessary to reduce the thickness of the gate oxide and the line widths of the gate electrodes and other interconnect lines connected to the MOS devices. Moreover, to achieve reliable operation of such reduced size devices, it is necessary to reduce the voltages at which these devices operate.
For example, in a 256-Mb dynamic random access memory (DRAM), it is typically necessary to reduce the external power supply voltage of about 3.3 volts, which is applied to the memory IC, to an internal voltage of about 1.5 volts (i.e., IVC=1.5 volts) in order to obtain reliable operation. However, as will be understood by those skilled in the art, decreasing the operating voltage typically reduces the sensing, amplification, and drive capability of sense amplifiers used to sense data stored in memory cell and limits the degree to which the sense amplifiers can adequately refresh memory cells after a read operation.
FIG. 1 shows the structure of a memory cell array and the peripheral circuits required for read and write operations in a conventional dynamic random access memory device. Each memory cell MC includes an access transistor 10 which serves as a switch, and a capacitor 12 which holds a bit of data. The gates of the access transistors 10 which are arranged in the same row are connected to a common word line WLi, where i=(1, 2, 3, . . . , n). The sources of the access transistors 10 which are arranged in a column are connected to alternate lines of a bit line pair BLj and BLjB, where j=(1, 2, . . . , m). One electrode of each capacitor 12 is connected to the drain of the corresponding access transistor 10, while the other electrode is connected to receive a plate voltage V.sub.P.
When a row address is supplied, it is decoded by a row decoder 14 into a row address signal, and one word line corresponding to the decoded row address is activated, thus turning on all the access transistors 10 connected to the activated word line. The stored charge on all the capacitors 12 corresponding to the activated word line flow onto the bit lines coupled to the capacitors 12. Owing to the relatively low capacitance of the capacitors 12 used in the memory device, sense amplifier circuits 16 are used to amplify the slight effect which the capacitor has on the bit line pair. Each of the sense amplifier circuits 16 draws the potential of the bit line having the lowest voltage to VSS, and raises the potential of the bit line having the higher voltage up to IVC. Only one of the amplified signals passes through the I/O gate circuit 20 corresponding to a decoded column address from column decoder 18.
FIG. 2 is a circuit diagram of a conventional sense amplifier circuit 16 associated with one of the memory cells of FIG. 1. Sense amplifier circuit 16 includes a pair of bit lines BL and BLB, a bit line equalization circuit 26, a sense amplifier 28, a column select gate 30, a sense amplifier equalization circuit 32, and a sense amplifier activating circuit 34. The bit lines BL and BLB, to which data is transferred, are connected to the memory cell MC. Each memory cell MC has an access transistor 10 coupled to a word line and a bit line, and a capacitor 12 coupled between the access transistor 10 and the plate voltage V.sub.P.
The bit line equalization circuit 26 receives a precharge voltage VBL and equalizes the bit lines BL and BLB to the precharge voltage level before a read operation or a write operation is performed. The sense amplifier 28 differentially amplifies the data transferred from the memory cell MC to the bit lines BL and BLB. The column select gate 30 connects the bit lines BL and BLB to the input/output lines IO and IOB in response to the column select line signal CSL. The sense amplifier equalization circuit 32 equalizes the sense amplifier nodes to the precharge voltage VBL. Once equalized, P-type sense amplifier and N-type sense amplifier latch enable signals LA and LAB, which control the sense amplifier 28, are activated as a result of the sense amplifier activating circuit 34, which is connected to the sense amplifier equalization circuit 32 and receives the sense amplifier activating signal LAPG and LANG.
The bit line equalization circuit 26 has three NMOS transistors M1, M2 and M3 connected between the bit lines BL and BLB. The transistors M1, M2 and M3 have gate electrodes for receiving a bit line equalization signal PEQ. Further, the precharge voltage VBL is input to the source electrodes of the NMOS transistors M1 and M2. The sense amplifier 28 is comprised of a P-type sense amplifier and an N-type sense amplifier. The P-type sense amplifier has PMOS transistors M4 and M5 which are connected in series between the bit lines BL and BLB. The P-type sense amplifier latch enable signal LA is input to the commonly connected source electrodes of the PMOS transistors M4 and M5, with the gate electrodes of the PMOS transistors M4 and M5 connected to the bit lines BL and BLB, respectively. The N-type sense amplifier has two NMOS transistors M6 and M7 connected in series to the bit lines BL and BLB. The N-type sense amplifier latch enable signal LAB is input to the commonly connected source electrodes of the NMOS transistors M6 and M7. The gates of transistors M6 and M7 are connected to the bit lines BL and BLB, respectively.
The column select gate 30 has two NMOS transistors M8 and M9 whose gate electrodes are coupled to the column select line CSL. The transistors M8 and M9 connect the bit lines BL and BLB to the input/output lines IO and IOB under control of the column select line CSL. The sense amplifier equalization circuit 32 has three NMOS transistors M10, M11 and M12 whose gate electrodes are collectively connected to a latch enable equalization signal PLAEQ. The sense amplifier activating circuit 34 has PMOS and NMOS transistors M13 and M14. The PMOS transistor M13 has its gate electrode connected to a P-type sense amplifier activating signal LAPG and its current path formed between the signal line LA and the internal power supply voltage IVC. The NMOS transistor M14 whose gate electrode is connected to a N-type sense amplifier activating signal LANG, has its current path formed between the signal line LAB and VSS.
FIG. 3A is an example of the bit line equalization signal generator 22 illustrated in FIG. 1. The bit line equalization signal generator 22 as shown in FIG. 3A has a PMOS transistor M15 and an NMOS transistor M16 which are connected in series between the internal power supply voltage IVC and the ground voltage VSS and have their gate electrodes commonly connected to a control signal PBLS. The bit line equalization signal PEQ is maintained at the level of the ground voltage VSS or the internal power supply voltage IVC according to the logic level of the control signal PBLS.
FIG. 3B is an example of the latch enable equalization signal generator 24 illustrated in FIG. 1. The latch enable equalization signal generator 24 has a PMOS transistor M17 and an NMOS transistor M18 which are connected in series between the internal power supply voltage IVC and the ground voltage VSS. The gate electrodes of the transistors M17 and M18 are commonly connected to the control signal PBLS. The control signal PBLS is used as a block select signal and determines whether a corresponding sense amplifier is enabled.
When cell data is at a "1" level for the memory cell MC and the word line WL is enabled, the voltage level of the bit line BL is raised by .DELTA.VBL due to charge sharing between the bit line BL and the cell capacitor 12. After the charge sharing is completed, if the N-type sense amplifier activating signal LANG is changed from the low level to the high level, the voltage level of the N-type sense amplifier enable signal LAB is lower than the level of the precharge voltage and the NMOS transistors M6 and M7 turn on and perform a sensing operation. Since the voltage level of the bit line BL is higher than that of the bit line BLB, the transistor M7 is thus turned on much more than transistor M6, which causes the bit line BLB to fall to a lower voltage level while the level of the bit line BL remains at its level of 1/2IVC+.DELTA.VBL.
As the voltage level of the bit line BLB falls, the P-type sense amplifier activating signal LAPG is changed from the high level to the low level and the PMOS transistor M13 is thus turned on, so that the PMOS transistors M4 and M5 are turned on. At this time, since the PMOS transistor M4 is more easily turned on than the PMOS transistor M5, the difference between the voltages of the bit lines BL and BLB increases. During a read operation, once the voltage difference between the bit lines BL and BLB is more than a certain level, the column select line CSL is enabled to the high level and the NMOS transistors M8 and M9 are turned on. The bit lines BL and BLB are thus connected to the input/output lines IO and IOB and the bit line data is transferred to the input/output line.
If the bit line equalization signal PEQ is driven at the voltage level of the internal power supply voltage IVC, the bit lines BL and BLB, which initially are at the internal power supply voltage IVC and the ground voltage VSS, are equalized by the NMOS transistors M1, M2 and M3 to the precharge voltage VBL (typically 1/2IVC). The internal power supply voltage IVC is used rather than the external power supply voltage EVC to reduce operating current and noise. Similarly, when the latch enable equalization signal PLAEQ is driven at the voltage level of the internal power supply voltage IVC, the NMOS transistors M10, M11 and M12 operate, and the source electrodes of transistors M4, M5, M6, and M7, that is, the sense amplifier nodes, are also equalized to the precharge voltage VBL. In a semiconductor memory device using an external power supply voltage EVC of 5V or 3.3V, the internal power supply voltage IVC is generally about 2.8V-3V and the level of the precharge voltage VBL is about 1.4V-1.5V. With voltages at these levels, there is typically no problem with the equalization operation.
However, if the level of the internal power supply voltage IVC is lowered in response to a lowering of the external power supply voltage EVC (for example, to about 2V), the internal power supply voltage IVC becomes about 1V. If these voltage levels are used, problems arise if the equalization circuits 26 and 32 previously described are used. At these voltages, the threshold voltage of NMOS transistor M3 of the bit line equalization circuit 26 becomes more than about 1V due to the body effect. Therefore, as the bit line BLB arrives at the precharge voltage VBL, the drain-source voltage Vds becomes small and the NMOS transistor M3 is almost turned off, so that it is difficult to smoothly perform a charge sharing operation.
Further, a gate-source voltage Vgs of the NMOS transistor M1 becomes almost 1V which prevents the NMOS transistor M1 from assisting with the equalization of the bit line BL. The NMOS transistor M2 and the sense amplifier equalization circuit 32 suffer the same problems and cannot perform the desired equalization operation properly. Further, if the equalization time of the bit lines BL and BLB and the equalization time of the P-type sense amplifier and N-type amplifier latch enable signals LA and LAB are extended in order to compensate for the inefficiency of the equalization of these voltage levels, the row precharge time (tRP) of the DRAM device becomes too long, thereby making it difficult to realize a high-speed access.